My invention relates to digital signal processing systems and more particularly to arrangements for clocking digital signals subject to timing variations.
Data processing and communication systems generally comprise groups of interconnected modules each of which contains one or more circuit units. In frequency synchronous clocking arrangements, the clock operates at a predetermined frequency and is used to coordinate the processing operations that take place in the different modules. The clock operating rate is fixed but the relative timing between the clock and digital signals at various locations in the system module can differ significantly. As is well known in the art, propagation time variations in both the clock and signal distribution cause significant differences in the phasing between signal and clock pulses in transfers from module to module and from circuit unit to circuit unit within a module. The difference in phasing or skewing of data signal timing with respect to the clock may be overcome by retiming or clocking the digital signals subjected to timing variations at prescribed points as the digital signals are transferred from one portion to another portion of the system. The clocking of digital signals at selected points in the modules re-establishes the proper phase relationship between the digital signals and the clock pulses so that skewing is eliminated.
Skew in the aforementioned digital signal processing systems is generally the result of propagation time variations which occur between integrated circuit chips due to manufacturing process tolerances and propagation time variations in varying length paths for signals and clocking pulses. One way known to minimize skew disclosed in U.S. Pat. No. 4,447,870 issued to S. A. Tague et al May 8, 1984 and elsewhere is dependent on the manual adjustment of the clock distribution system. Such manual or operator controlled adjustment requires considerable time, effort and expense and must be repeated if components of the system are changed.
U.S. Pat. No. 4,482,819 issued to B. J. Oza et al Nov. 13, 1984 discloses a data processor system clock checking circuit in which a central clock generator generates a plurality of odd and even clock pulses which are distributed to a plurality of modules on equal length lines and a plurality of gate pulses on varying length lines. A detection circuit at a module detects if the gate pulse and the clock pulse begin and end in proper sequence and provides an indication of an improper sequence. The processor system may be stopped on occurrence of an improper sequence indicating signal. The arrangement, however, does not automatically correct skew between data signals incoming to a module and the module clock.
U.S. Pat. No. 4,479,216 issued to R. H. Kramback et al on Oct. 23, 1984 discloses a skew-free clock circuit for integrated circuit chips in which an op-amp feedback arrangement is used to provide non-skewed clock pulses from a source of skewed clock pulses. Skew in the clock-in pulses results in a change in the average voltage of the output clock pulse which average voltage is compared to a reference. A control signal obtained from the comparison, adjusts the average voltage of at the output. The operation of the feedback and comparison circuit, however, may not be sufficiently fast to accommodate rapid and variable changes in signals.
Another solution to clock skew disclosed in U.S. Pat. No. 4,637,018 issued Jan. 13, 1987 to L. P. Flora et al employs feedback circuitry including a multi-tapped delay line and an accurate constant delay in conjunction with a phase comparator for automatically adjusting the chip propagation delay of each clock distribution chip to provide substantially the same constant predetermined delay relative to the main-system clock for the output clocks provided by the clock distribution system. The circuit arrangement to accomplish such automatic adjustment, however, is complex, and does not operate well in equipment where propagation delays of the data signals are highly uncertain. It is an object of the invention to provide an improved skew compensation circuit that rapidly accommodates highly variable skew between data signals and clock pulses.